Digital components, such as sequential state elements, are typically used store data generated by a functional logic block and then pass the data to another functional logic block within an integrated circuit (IC). In order to test the functionality of the digital circuit, the sequential state elements need to be capable of scanning known test information into the sequential state elements in order to determine if the pipeline circuit and the pipeline stages are operating correctly.
Scanning is therefore an important and often indispensable mechanism for testing the operation of digital circuits. Unfortunately, scanning mechanisms often introduce a significant amount of complexity into a sequential state element as well as presenting other disadvantages. For example, scanning require separate scan clock signals to operate appropriately during testing to prevent hold time violations. This can significantly complicate clock routing in the digital circuit. Additionally, when designing ICs, computer aided design tools have to optimize timing not only for normal operations but also for the scanning mechanism. This can lead to timing inefficiencies in the designed IC. Therefore what is needed are scanning mechanisms that introduce less complexity and timing inefficiencies into an IC.